This decision is usually made on BOM cost and paid for in schedule. It is a three-variable decision — BOM, NRE, and time to production — and the middle one is almost always under-estimated.
Bestom engineering note — written by our own design and BSP engineers from work on Rockchip platforms. Platform parameters quoted here are taken from our published datasheets; see Core Boards & SoM. For translated community notes, see the Tech Notes index.
| SoM + carrier board | Full custom board | |
|---|---|---|
| BOM | Higher per unit — you buy the module, the connector and the carrier | Lower per unit at volume — you buy the SoC, DDR, eMMC and passives |
| NRE | Lower — DDR routing, power sequencing and SoC bring-up are already done and validated | Higher — high-speed DDR layout, power tree, SI/PI, thermal, and bring-up are all yours |
| Time to first working prototype | Weeks — carrier design only | Months — including a DDR bring-up learning curve |
| Mechanical freedom | Bounded — the SoM footprint and connector height are fixed | Complete — you own the whole outline and stack-up |
| Supply risk | Partly transferred to the module supplier | Entirely yours |
| Re-spin cost | Cheaper — usually the carrier only | Expensive — potentially the whole board |
The break-even is volume × the BOM delta, measured against the NRE delta and the schedule delta. Teams routinely compute the first term and skip the other two.
When the product is an integration job — the value is in the software, the enclosure and the channel, not in the board. A finished main board with the I/O already populated removes the carrier design entirely. This is a legitimate engineering choice, not a compromise.
When the product does one thing — audio, a small HMI, sensing — a dedicated SoC (RK3506G2 class, or RK2108D for audio/voice) usually beats a shrunk application processor on unit cost, power budget and boot time.
| Phase | SoM + carrier | Full custom board |
|---|---|---|
| Requirement lock and platform choice | shared | shared |
| Schematic | carrier only | full system |
| Layout | carrier; no DDR routing | full system including high-speed DDR |
| Bring-up | carrier peripherals; the SoC is proven | power sequencing, DDR training, all peripherals |
| Thermal validation | carrier + enclosure | full system |
| Certification | shared | shared |
The row that moves the schedule is layout. Not because layout is slow in general, but because high-speed DDR layout on a from-scratch board is where designs go back for a second and sometimes third revision. A validated module removes that entire risk category from your first product.
A pattern that works well: ship product generation 1 as a carrier around a validated module to hit the window and learn the market; move to a custom board for generation 2 with real volume data and a frozen feature set. You keep the schedule and still capture the BOM saving — just one generation later, when you actually know the volume.
Work the constraint funnel before comparing platforms.
Read nextIf you are going custom, lock these first.
Read nextM88 / M76 / M68 / M66 / B66 / M506 / M08D with grades and mechanicals.
Send us the product spec or the constraint list. We design and develop custom hardware on Rockchip platforms — and we will tell you if the platform you have in mind is the wrong one.
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